Advertisement

Applied Physics A

, 125:682 | Cite as

Analytical modeling of threshold voltage and subthreshold swing in Si/Ge heterojunction FinFET

  • Rajashree DasEmail author
  • Srimanta Baishya
Article
  • 29 Downloads

Abstract

This paper presents an analytical model of threshold voltage (Vth) and subthreshold swing (S) for a tri-gate (TG) heterojunction n-FinFET. The heterojunction is formed between the silicon source and germanium channel. The electrical parameters are analyzed by solving three-dimensional (3-D) Poisson’s equation with the aid of superposition principle. Based on the 3-D potential function and the minimum potential position in the channel, Vth and S are modeled. The model is validated against TCAD simulations. The modeled Vth and S are verified for variation of channel length (Lf), workfunction, oxide thickness (tox), drain-to-source voltage (VDS), gate-to-source voltage (VGS), channel concentration and fin width (Tfin). The models developed for Vth and S in the TG heterojunction FinFET are evaluated for its homojunction equivalent silicon structure, and found to exhibit excellent agreement with TCAD results.

Notes

Acknowledgements

This work is an outcome of project under CSIR-EMR-II (Sanction No. 22 (0737)17/EMR-II), Govt. of India awarded to Electronics and Communication Engineering department, NIT Silchar.

References

  1. 1.
    X. Huang, W.C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.K. Choi, K. Asano, V. Subramanian, T.J. King, J. Bokor, C. Hu, Sub 50-nm FinFET: PMOS (Int. Electron Devices Meeting Technical Dig, Washington, 1999), pp. 67–70Google Scholar
  2. 2.
    X. Huang, W.C. Lee, C. Kuo, D. Hisamoto, L. Chang, J. Kedzierski, E. Anderson, H. Takeuchi, Y.K. Choi, K. Asano, V. Subramanian, T.J. King, J. Bokor, C. Hu, Sub-50 nm P-channel FinFET. IEEE Trans Electron Devices 48, 880–886 (2001)ADSCrossRefGoogle Scholar
  3. 3.
    D. Hisamoto, W.C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.J. King, J. Bokor, C. Hu, FinFET-a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Devices 47, 2320–2325 (2000)ADSCrossRefGoogle Scholar
  4. 4.
    G. Pei, J. Kedzierski, P. Oldiges, M. Ieong, E.C.C. Kan, FinFET design considerations based on 3-D simulation and analytical modeling. IEEE Trans Electron Devices 49, 1411–1419 (2002)ADSCrossRefGoogle Scholar
  5. 5.
    Y. Li, H.M. Chou, J.W. Lee, Investigation of electrical characteristics on surrounding-gate and omega-shaped-gate nanowire FinFETs. IEEE Trans. Nanotechnol 4, 510–516 (2004)ADSCrossRefGoogle Scholar
  6. 6.
    K.M. Tan, T.Y. Liow, R.T.P. Lee, K.M. Hoe, C.H. Tung, N. Balasubramanian, G.S. Samudra, Y.C. Yeo, Strained p-channel FinFETs with extended Π-shaped silicon-germanium source and drain stressors. IEEE Electron Device Lett 28, 905–908 (2007)ADSCrossRefGoogle Scholar
  7. 7.
    C.T. Chung, C.W. Chen, J.C. Lin, C.C. Wu, C.H. Chien, G.L. Luo, C.C. Kei, C.N. Hsiao, Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High I ON/ I OFF ratio Ge FinFETs. IEEE Trans Electron Devices 60, 1878–1883 (2013)ADSCrossRefGoogle Scholar
  8. 8.
    V.K. Mishra, R.K. Chauhan, Impact of Ge substrate on drain current of trigate N-FinFET, in Int. Conference Adv. Comput. Commun. Inform. (ICACCI), pp 1976–1980 (2014)Google Scholar
  9. 9.
    D. Connelly, P. Zheng, T.J.K. Liu, Channel stress and ballistic performance advantages of gate-all-around fets and inserted-oxide FinFETs. IEEE Trans Nanotechnol 16, 209–216 (2017)ADSCrossRefGoogle Scholar
  10. 10.
    S.J. Chang, H. Zhou, N. Gong, D.M. Kang, J.W. Lim, M. Si, P.D. Ye, T.P. Ma, Fin-width effects on characteristics of InGaAs-based independent double-gate FinFETs. IEEE Electron Device Lett. 38, 441–444 (2017)ADSCrossRefGoogle Scholar
  11. 11.
    H. K. Jung, Threshold voltage depndence on bias for FinFET using analytical potential model. J Inform Commun Converg Eng 8, 107–111 (2010)CrossRefGoogle Scholar
  12. 12.
    N. Fasarakis, A. Tsormpatzoglou, D.H. TaSis, C.A. Dimitriadis, K. Papathanasiou, J. Jomaah, G. Ghibaudo, Analytical unified threshold voltage model of short-channel FinFETs and implementation. Solid State Electron 64, 34–41 (2011)ADSCrossRefGoogle Scholar
  13. 13.
    G. Katti, N. DasGupta, A. DasGupta, Threshold Voltage model for mesa-isolated small geometry fully depleted SOI MOSFETs based on analytical solution of 3-D Poisson's equation. IEEE Trans. Electron Devices. 51, 1169–1177 (2004)ADSCrossRefGoogle Scholar
  14. 14.
    D.S. Havaldar, G. Katti, N. DasGupta, A. DasGupta, Subthreshold current model of FinFETs based on analytical solution of 3-D Poisson's equation. IEEE Trans. Electron Devices. 53, 737–742 (2006)ADSCrossRefGoogle Scholar
  15. 15.
    L. Armelao, M. Fabrizio, S. GroS, A. Martucci, E. Tondello, Molecularly interconnected SiO2–GeO2 thin films: sol–gel synthesis and characterization. J. Mater. Chem. 10, 1147–1150 (2000)CrossRefGoogle Scholar
  16. 16.
    T. Busani, H. Plantier, R.A.B. Devine, C. Hernandez, Y. Campidelli, Growth and characterization of GeO2 films obtained by plasma anodization of epitaxial Ge films. J Appl Phys 85, 4262–4264 (1999)ADSCrossRefGoogle Scholar
  17. 17.
    T. Lange, W. Njoroge, H. Weis, M. Beckers, M. Wuttig, Physical properties of thin GeO2 films produced by reactive DC magnetron sputtering. Thin Solid Films 365, 82–89 (2000)ADSCrossRefGoogle Scholar
  18. 18.
    N. Terakado, K. Tanaka, Photo-induced phenomena in sputtered GeO2 films. J Non-Cryst Solids 351, 54–60 (2005)ADSCrossRefGoogle Scholar
  19. 19.
    K. Kurosawa, Y. Maezono, J.-I. Miyano, T. Motoyama, A. Yokotani, GeO2 and SiO2 thin film preparation with CVD using ultraviolet excimer lamps. J Phys IV France 11, Pr3–739-Pr3–745 (2001).Google Scholar
  20. 20.
    A. Sharma, A.A. Goud, K. Roy, Sub-10 nm FinFETs and tunnel-FETs: from devices to systems, in 2015 design, automation and test in Europe Conference and Exhibition (DATE), Grenoble, pp 1443–1448 (2015)Google Scholar
  21. 21.
    S. Sinha, G. Yeric, V. Chandra, B. Cline, Y. Cao, Exploring sub-20nm FinFET design with predictive technology models, in DAC design automation conference, San Francisco, pp 283–288 (2012)Google Scholar
  22. 22.
    Matlab 2013a, The MathWorks, Natick (2013)Google Scholar
  23. 23.
    Synopsys TCAD Sentaurus Device Manual (Synopsys Inc, Mountain View, 2012)Google Scholar
  24. 24.
    Y. Tsividis, C.M. Andrew, The four-terminal MOS transistor. Operation and modeling of the MOS transistor, 3rd ed. (McGraw-Hill, New York, 2011, pp. 151–242Google Scholar
  25. 25.
    H.A. El Hamid, J.R. Guitart, V. Kilchytska, D. Flandre, B. Iniguez, IEEE Trans Electron Devices A 3-D analytical physically based model for the subthreshold swing in undoped trigate FinFETs. 54, 2487–2496 (2007)ADSCrossRefGoogle Scholar
  26. 26.
    M.Mustafa, T.A. Bhat, M.R. Beigh, World J Nano Sci Eng Threshold voltage sensitivity to metal gate work-function based performance evaluation of double-gate n-FinFET structures for LSTP technology. 3, 17–22 (2013)CrossRefGoogle Scholar
  27. 27.
    A. Godoy, J.A.L. Villanueva, J.A.J. Tejada, A. Palma, F. Gamiz Solid State Electron A simple subthreshold swing model for short channel MOSFETs. 45, 391–397 (2001)ADSCrossRefGoogle Scholar
  28. 28.
    Q. Chen, B. Agrawal, J.D. Meindl, A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs. IEEE Trans. Electron Devices. 49, 1086–1090 (2002)ADSCrossRefGoogle Scholar
  29. 29.
    R. Das, R. Goswami, S. Baishya, Tri-gate heterojunction SOI Ge-FinFETs. Superlattices Microstruct. 91, 51–61 (2016)ADSCrossRefGoogle Scholar

Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringNIT SilcharSilcharIndia

Personalised recommendations