Applied Physics A

, 125:813 | Cite as

Nanocantilever tri-gate junctionless cuboidal nanowire-FET-based directional pressure sensor

  • Aman Aggarwal
  • Ashish RamanEmail author
  • Naveen Kumar
  • Sarabdeep Singh


This paper proposes a designing of a directional pressure sensor based on NEMS nanocantilever structure embedded on uniformly and highly doped junctionless triple gate (TG) cuboidal nanowire-FET (TG-JL NWFET) device. In the designed device, each gate electrode is used as nanocantilever beam structure and the magnitude of pressure on the cantilever is measured by observing different electrical characteristics on bending of the cantilever beam, i.e., for 0 nm, 0.90 nm and 1.75 nm bending of the cantilever, respectively. To detect the direction of pressure, the performance of the pressure sensor for bending in single, dual and triple directions is compared with each other. In single direction bending, the top of the cantilever completely bends and the rest of the cantilevers remain in an equilibrium position. In the dual direction, bending right and left cantilevers are completely bent and the top cantilevers remain in an equilibrium position; in triple bending, all the three cantilevers completely bend simultaneously. The device parameters such as electric field, energies of conduction and valence band and recombination rate are observed to study the device physics. ON to OFF current ratio, threshold voltage, drain-induced barrier leakage and subthreshold slope are used as performance parameters for analyzing the performance of single, dual and triple direction bending with respect to different bending of the cantilever. The ON current obtained for triple direction bending is 14.7 and 12.5% higher than the dual direction and single direction bending of the cantilever, respectively.



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Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  • Aman Aggarwal
    • 1
  • Ashish Raman
    • 1
    Email author
  • Naveen Kumar
    • 1
  • Sarabdeep Singh
    • 1
  1. 1.VLSI Design Lab., Department of Electronics and CommunicationsDr BR Ambedkar National Institute of TechnologyJalandharIndia

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