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Applied Physics A

, 125:173 | Cite as

Design and analysis of logic inverter using antimonide-based compound semiconductor junctionless transistor

  • Min Su Cho
  • Young Jun Yoon
  • Seongjae Cho
  • In Man KangEmail author
Article
  • 9 Downloads

Abstract

In this paper, the optimization of gallium antimonide (GaSb) junctionless field-effect transistor (JLFETs) and logic inverter characteristics are analyzed. The hole mobility of GaSb is much higher than that of Si, which warrants high-performance p-channel transistor and low-power operation capability, and also, the mismatch between electron and hole mobilities is much lessened. Consequently, the dimension of p-channel MOSFET based on GaSb can be significantly reduced compared with the Si case. For these reasons and the potential application of GaSb to wide variety of III–V compound semiconductors towards electronics and photonics integration, and components under the extreme conditions, GaSb JLFET is studied in depth in this work. The proposed GaSb JLFET has the Al2O3 buffer between the channel and the Si substrate, which releases the lattice mismatch and suppresses leakage current effectively. The proposed n-channel JLFET has an Ion of 472 µA/µm and, SS of 76.2 mV/dec. The p-channel JLFET has an Ion of 541 µA/µm and SS of 73.4 mV/dec. The inverter using GaSb JLFETs shows excellent performances including NML = 0.28 V, NMH = 0.29 V, τPHL of 1.8 ps, and τPLH of 6.8 ps at an operating voltage as low as VDD = 0.7 V.

Notes

Acknowledgements

This work was supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science, ICT & Future Planning (2016R1C1B2015979) and in part by Samsung Electronics Co. Ltd. This study was also supported by the BK21 Plus project funded by the Ministry of Education, Korea (21A20131600011). This work was also supported by the Ministry of Trade, Industry & Energy (MOTIE) (10080513) and Korea Semiconductor Research Consortium (KSRC) support program for the development of the future semiconductor devices. This work was supported by NRF Grant funded by Government (NRF-2018H1A2A1063117-Global Ph. D. Fellowship Program). The EDA tool was supported by the IC Design Education Center (IDEC), Korea.

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Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2019

Authors and Affiliations

  • Min Su Cho
    • 1
  • Young Jun Yoon
    • 1
  • Seongjae Cho
    • 2
  • In Man Kang
    • 1
    Email author
  1. 1.School of Electronics EngineeringKyungpook National UniversityDaeguRepublic of Korea
  2. 2.Department of Electronic EngineeringGachon UniversitySeongnamRepublic of Korea

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