Applied Physics A

, 124:838 | Cite as

Low-frequency noise analysis of heterojunction SELBOX TFET

  • P. GhoshEmail author
  • B. Bhowmick


This paper explores low-frequency noise analysis of TFET on selective buried oxide (SELBOX) with a δp + silicon germanium layer at the source channel junction in the presence of uniform and gaussian trap concentrations. Different electrical parameters of the proposed structure for the optimized position of gap are investigated. Lowest OFF current is obtained for the position of gap near the source region. Considering the current noise spectral density (SID) and voltage noise spectral density (SVG), the impact of noise on the device performance is analyzed. Noise spectral densities are compared in the presence of interface trap concentrations and δp+ Si1−xGex layer Ge-mole fractions. Variation of noise densities with frequency is explored. Improved ION/IOFF ratio and subthreshold swing are obtained in the presence of uniform trap as compared to gaussian trap.


  1. 1.
    K. Boucart, A.M. Ionescu, Double-gate tunnel FET With High-k gate dielectric. IEEE Trans. Electron Devices 54, 1725–1733 (2007). ADSCrossRefGoogle Scholar
  2. 2.
    K. Sivasankaran, P.S. Mallick, A comparative study of radio frequency stability performance of double gate MOSFET and double gate tunnel FET, Proc 013 Int Conf Green Comput Commun Conserv Energy, ICGCE, 220–224, (2013)Google Scholar
  3. 3.
    A. Pal, A.K. Dutta, Analytical drain current modeling of double-gate tunnel field-effect transistors. IEEE Trans. Electron Devices 63, 3213–3221 (2016)ADSCrossRefGoogle Scholar
  4. 4.
    K.K. Young, Short-channel effect in fully depleted SOIMOSFETs. Electron devices. IEEE Trans. Electron Devices 36, 2–5 (1989). CrossRefGoogle Scholar
  5. 5.
    A. Chaudhry, M.J. Kumar, Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability, a review. IEEE Trans. Device Mater. Reliab. 4, 99–109 (2004). CrossRefGoogle Scholar
  6. 6.
    B. Bhushan, K. Nayak, V.R. Rao, DC compact model for SOI tunnel field-effect transistors. IEEE Trans. Electron Devices 59, 2635–2642 (2012). ADSCrossRefGoogle Scholar
  7. 7.
    R. Goswami, B. Bhowmick, Circular gate tunnel FET: ‘optimization and noise analysis’. Proc. Comput. Sci. 93, 125–131 (2016)CrossRefGoogle Scholar
  8. 8.
    R. Goswami, B. Bhowmick, S. Baishya, Electrical noise in circular gate tunnel FET in presence of interface traps. Superlattices Microstruct. 86, 342–354 (2015)ADSCrossRefGoogle Scholar
  9. 9.
    S.K. Mitra, R. Goswami, B. Bhowmick, A hetero dielectric stack gate SOI-TFET with back gate and its application as a digital inverter. Superlattices Microstruct. 92, 37–51 (2016)ADSCrossRefGoogle Scholar
  10. 10.
    S. Ahish, D. Sharma, M.H. Vasantha, Y.B.N. Kumar, Design and analysis of novel InSb/Si heterojunction DoubleGate tunnel field effect transistor. IEEE Comput. Soc. Annu. Symp. VLSI. 105–109, (2016).
  11. 11.
    N.B. Balamurugan, G.L. Priya, S. Manikandan, G. Srimathi, Analytical modeling of dual material gate all around stack architecture of tunnel FET. in Proc IEEE Int Conf VLSI Des, March, 294–299, (2016).
  12. 12.
    N.N. Mojumder, K. Roy, ‘Band-to-band tunneling ballistic nanowire FET: circuit-compatible device modeling and design of ultra-low-power digital circuits and memories. IEEE Trans. Electron Devices 56, 2193–2201 (2009). ADSCrossRefGoogle Scholar
  13. 13.
    Y. Lv, Q. Huang, H. Wang et al., A numerical study on graphene nanoribbon heterojunction dual-material gate tunnel FET. IEEE Electron Device Lett. 37, 1354–1357 (2016). ADSCrossRefGoogle Scholar
  14. 14.
    R. Pandey, B. Rajamohanan, H. Liu, V. Narayanan, S. Datta, Electrical noise in heterojunction interband tunnel FETs. IEEE Trans. Electron Devices 61, 552–560 (2014)ADSCrossRefGoogle Scholar
  15. 15.
    F.S. Neves, P.G.D. Agopianand, J.A. Martino, B. Cretu, R. Rooyackers, A. Vandooren, E. Simoen, A.V. Thean, C. Claeys, Low-frequency noise analysis and modeling in vertical Tunnel FETs with Ge source. IEEE Trans. Electron Devices. 63, 1658–1665, (2016). ADSCrossRefGoogle Scholar
  16. 16.
    W.Y. Choi, W. Lee, Hetero-gate-dielectric tunneling field-effect transistors. IEEE Trans. Electron Devices. 57, 2317–2319 (2010). ADSCrossRefGoogle Scholar
  17. 17.
    D. Barah, A.K. Singh, B. Bhowmick, TFET on selective buried oxide (SELBOX) substrate with improved I ON/I OFF ratio and reduced ambipolar current. Silicon (2018). CrossRefGoogle Scholar
  18. 18.
    M. Narayanan, H. Al-Nashash, M. Baquer, D. Pal, M. Chandra, Analysis of kink reduction in SOI MOSFET using selective back oxide structure, active and passive electronic components. 565827, 1–9 (2012)Google Scholar
  19. 19.
    T.C.A.D. Synopsys, Manual, ver. E2010.12Google Scholar
  20. 20.
    A. Biswas, S.S. Dan, C.L. Royer, W. Grabinski, A.M. Ionescu, TCAD simulation of SOI TFETs and calibration of non-local band-to-band tunneling model. Micro Electron. Eng. 98, 334–337 (2012)CrossRefGoogle Scholar
  21. 21.
    X.Y. Huang et al., Effect of interface traps and oxide charge on drain current degradation in tunneling field-effect transistors. IEEE Electron Device Lett. 31, 779–781 (2010)ADSCrossRefGoogle Scholar
  22. 22.
    Q. Huang, R. Huang, C. Chen, C. Wu, J. Wang, C. Wang et al. Deep insights into low frequency noise behavior of tunnel FETs with source junction engineering, Symposium on VLSI Technology: Digest of Technical Papers, pp 70–71, (2014)Google Scholar

Copyright information

© Springer-Verlag GmbH Germany, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringNIT SilcharSilcharIndia

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