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High Performance Four-Quadrant Analog Multiplier Using DXCCII

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Abstract

This paper presents a four-quadrant analog multiplier using a single dual-X second-generation current conveyor (DXCCII). The proposed analog multiplier employs two NMOS transistors operating in triode region, besides a single DXCCII. The performances of the proposed analog multiplier are verified through PSPICE simulation using 0.18 μm TSMC CMOS process parameters. Simulation results reveal that the circuit has a − 3 dB bandwidth of 19.30 GHz and 0.79% total harmonic distortion for the input voltage of 250 mV. The application of proposed analog multiplier as a squarer, for amplitude modulation and as frequency doubler are also included. The detailed comparisons with existing literature justify the novelty of the proposed circuit.

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Acknowledgements

The authors thank anonymous reviewers and the EIC, Prof. MNS Swamy, for recommending this paper.

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Correspondence to Sudhanshu Maheshwari.

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Rajpoot, J., Maheshwari, S. High Performance Four-Quadrant Analog Multiplier Using DXCCII. Circuits Syst Signal Process 39, 54–64 (2020). https://doi.org/10.1007/s00034-019-01179-x

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Keywords

  • Four-quadrant analog multiplier
  • Dual-X second-generation current conveyors (DXCCIIs)
  • Amplitude modulator (AM)
  • Squarer circuit
  • Frequency doubler