A 17-to-24 GHz Low-Power Variable-Gain Low-Noise Amplifier in 65-nm CMOS for Phased-Array Receivers
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This paper presents a low-power compact variable-gain low-noise amplifier that operates over the frequency band of 17–24 GHz. A design methodology is proposed to determine the optimal size of transistors to achieve the maximum possible gain for current-steering variable-gain amplifiers (VGAs). Moreover, the effect of gain switching on the input and output return losses of current-steering VGAs is analytically studied. Also, various structures of metal-oxide-metal capacitors are examined to find the optimal structure for high-frequency applications. A proof-of-concept VGA is fabricated in a 65-nm bulk CMOS process, and it is employed in a receiver chain. The designed VGA features about 13.3 dB maximum power gain with 5-bit resolution and an average noise figure of 3 dB. The achieved root-mean-square gain error is about 0.45 dB after the fabrication process. The output 1-dB compression point of the VGA is about − 1 dBm at the center of the frequency band. The VGA consumes about 4.2 mW from a 1-V supply, and excluding the pads, it occupies a silicon area of 0.23 mm2.
KeywordsBeamforming CMOS Current-steering Low-noise variable-gain amplifiers Low power MOM capacitors Mm-wave phased-array receivers Short-range radars
This work has been financially supported in part by Iran National Science Foundation (INSF).
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