Theory of Expansion Boolean Algebra and Its Applications in CMOS VLSI Digital Systems

  • En-hua JiangEmail author
  • Wen-bin Jiang


Based on the relationship between circuits (systems) and the signals in the circuits (systems), the theory of expansion Boolean algebra is presented in this paper. Static complementary logic circuits and static pass transistors logic circuits have been used to implement the high-speed and low-power-consumption cells circuits in CMOS VLSI systems. It is important to study the extraction method of logic expressions for these types of circuits. By analyzing the operations principles of MOS transistors in CMOS circuits, the theory of expansion Boolean algebra of CMOS logical circuits is presented. Based on the algebraic theory, a method of extracting the logic expressions from the two types of CMOS logical circuits is derived. On the basis of the method, a switch-level design method of CMOS logic circuits based on the algebra theory is presented, and the design method is used to design the high-speed and low-power full adder cells in CMOS VLSI systems. By the results of the simulation experiments, it is shown that the pass transistors and transmission gates hybrid CMOS full adder circuits proposed in this paper have a lower power-delay product by comparison with the full adder circuits designed by using other methods.


Expansion Boolean algebra CMOS digital circuit Full adder Switch-level expression Logic expression extraction VLSI design Full swing 



  1. 1.
    P. Bhattacharyya, B. Kundu, S. Ghosh, V. Kumar, A. Dandapat, Performance analysis of a low-power high-speed hybrid 1-bit full adder circuit. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 23(10), 2001–2008 (2015)CrossRefGoogle Scholar
  2. 2.
    S. Goel, A. Kumar, M.A. Bayoumi, Design of robust, energy-efficient full adders for deep-submicrometer design suing hybrid-CMOS logic style. IEEE Trans. VLSI Syst. 14(12), 1309–1321 (2006)CrossRefGoogle Scholar
  3. 3.
    J.P. Hayes, Pseudo-Boolean logic circuits. IEEE Trans. Comput. C-35(7), 602–612 (1986)CrossRefzbMATHGoogle Scholar
  4. 4.
    Y. Jiang, A. Al-Sheraidah, Y. Wing et al., A novel multiplexer-based low power full adder. IEEE Trans. Circuits Syst. II Express Briefs 51(7), 345–348 (2004)CrossRefGoogle Scholar
  5. 5.
    S. Kang, Y. Leblebigi, CMOS Digital Integrated Circuit: Analysis and Design, 3rd edn. (McGraw-Hill, New York, 2003)Google Scholar
  6. 6.
    H. Lee, G.E. Sobelman, New XOR/XNOR and full adder circuits for low-voltage low-power applications. Microelectron. J. 29(3), 509–517 (1998)Google Scholar
  7. 7.
    H. Naseri, S. Timarchi, Low-power and fast full adder by exploring new XOR and XNOR. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 26(8), 1481–1493 (2018)CrossRefGoogle Scholar
  8. 8.
    K. Navi, M. Maeen, V. Foroutan et al., A novel low power full-adder cell for low voltage. Integr. VLSI J. 42(4), 457–467 (2009)CrossRefGoogle Scholar
  9. 9.
    M. Pedran, X. Wu, A new description of CMOS circuits at switch-level. Proc. IEEE 1, 551–556 (1997). Google Scholar
  10. 10.
    C. Pedron, A. Stauffer, Analysis and synthesis of combinational pass transistor circuits. IEEE Trans. Comput. Aided Des. 7(7), 775–786 (1988)CrossRefGoogle Scholar
  11. 11.
    D. Radhakrishnun, Low voltage low power CMOS full adder. IEE Proc. Circuits Dev. Syst. 148(1), 19–24 (2001)CrossRefGoogle Scholar
  12. 12.
    A.M. Shams, M.A. Bayoumi, A novel high performance CMOS 1-bit full adder cell. IEEE Trans. Circuits Syst. II Analog Digit. Signal Process. 47(5), 478–481 (2000)CrossRefGoogle Scholar
  13. 13.
    A.M. Shams, T.K. Darwish, M.A. Bayoumi, Performance analysis of low-power 1 bit CMOS full-adder cells. IEEE Trans. Very Large Scale Integr. Syst. 10(1), 20–29 (2002)CrossRefGoogle Scholar
  14. 14.
    M.A. Valashani, S. Mirzakuchaki, A novel fast, low-power and high-performance XOR-XNOR cell, in Proceedings of the IEEE International Symposium Circuits System (ISCAS), Vol. 1 (2016), pp. 694–697Google Scholar
  15. 15.
    M. Vesterbacka, A 14-transistor CMOS full adder with full voltage-swing nodes, in Proceedings of the IEEE Workshop Signal Processing System (Sips) (1999), pp. 713–722Google Scholar
  16. 16.
    S. Wairya, R.K. Nagaria, S. Tiwari, New design methodologies for high-speed mixed-mode CMOS full adder circuits. Int. J. VLSI Des. Commun. Syst. (VLSICS) 2(2), 78–98 (2011)Google Scholar
  17. 17.
    R. Zimmermann, W. Fichtner, low-power styles: CMOS versus pass-transistor logic. IEEE J. Solid State Circuits 32(7), 1079–1090 (1997)CrossRefGoogle Scholar

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© Springer Science+Business Media, LLC, part of Springer Nature 2019

Authors and Affiliations

  1. 1.School of Physics and Electronic InformationHuaibei Normal UniversityHuaibeiChina

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