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A Novel Very Low-Complexity Multi-valued Logic Comparator in Nanoelectronics

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Abstract

Using multi-valued logic (MVL) can reduce chip connections, which can have a direct effect on the chip area and connections power consumption. In the recent years, due to the high capability of nanotechnology in designing MVLs, some researchers have focused on this field. In designing MVL circuits, the low-complexity design is of great importance to fulfill the MVL aim. In this paper, a very low-complexity comparator for the MVL is proposed based on the multi-threshold voltage in CNTFETs. The proposed comparator in the 1-bit greater function only needs four transistors for all multi-valued logics; this results in a considerable transistor count reduction in comparison with the pervious works relying on 32 and 50 transistors in a ternary to quaternary case, respectively. Also, the number of 1-bit comparators is reduced from 50 and 74 transistors for the ternary to quaternary cases in the previous works to 12 in the proposed design. Additionally, the multi-digit comparator using the novel digit comparator is proposed. The simulation results using the Stanford 32 nm CNTFET library in HSPICE confirm the proper operation of the proposed comparator with the same range in PDP, in comparison with the previous works.

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References

  1. 1.

    A. Akturk, G. Pennington, N. Goldsman, A. Wickenden, Electron transport and velocity oscillations in a carbon nanotube. IEEE Trans. Nanotechnol. 6(4), 469–474 (2007)

  2. 2.

    T. Araki, H. Tatsumi, M. Mukaidono, F. Yamamoto, Minimization of incompletely specified regular ternary logic functions and its application to fuzzy switching functions, in Proceedings of the IEEE International Symposium on Multiple-Valued Logic, (May 1998), pp. 289–296

  3. 3.

    P.C. Balla, A. Antoniou, Low power dissipation MOS ternary logic family. IEEE J. Solid-State Circuits 19(5), 739–749 (1984)

  4. 4.

    K.W. Current, Algorithmic analogue-to-quaternary converter circuit using current-mode CMOS. Electron. Lett. 28(12), 1111–1112 (1992)

  5. 5.

    K.W. Current, A CMOS quaternary threshold logic full adder circuit with transparent latch, in Proceedings of the International Symposium on Multiple-Valued Logic, (May 1990), pp. 168–173

  6. 6.

    K.W. Current, A CMOS quaternary latch. Electron. Len. 25(13), 856–858 (1989)

  7. 7.

    K.W. Current, Application of quaternary logic to the design of a proposed discrete cosine transform chip. Int. J. Electron. 67(5), 687–701 (1989)

  8. 8.

    K.W. Current, M.E. Hurlston, A bidirectional current-mode CMOS multiple-valued logic memory circuit, in Proceedings of the International Symposium on Multiple-Valued Logic, (May 1991), pp. 196–202

  9. 9.

    K.W. Current, F.A. Edwards, D.A. Freitas, A CMOS multiple valued logic test chip, in Proceedings of the International Symposium on Multiple-Valued Logic, (May 1987), pp. 16–19

  10. 10.

    K.W. Current, D.A. Freitas, F.A. Edwards, CMOS quaternary threshold logic full adder circuits. in Proceedings of the International Symposium on Multiple-Valued Logic, (May 1985), pp. 318–322

  11. 11.

    K.W. Current, Current-mode CMOS multiple-valued logic circuits. IEEE J. Solid-State Circuits 29(2), 95–107 (1994)

  12. 12.

    A. Daraei, S.A. Hosseini, Novel energy-efficient and high-noise margin quaternary circuits in nanoelectronics. AEU Int. J. Electron. Commun. 105, 145–162 (2019)

  13. 13.

    J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part I: model of the intrinsic channel region. IEEE Trans. Electron Device 54(12), 3186–3194 (2007)

  14. 14.

    J. Deng, H.-S.P. Wong, A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application—Part II: full device model and circuit performance benchmarking. IEEE Trans. Electron. Device 54(12), 3195–3205 (2007)

  15. 15.

    S.A. Ebrahimi, M.R. Reshadinezhad, A. Bohlooli, M. Shahsavari, Efficient CNTFET-based design of quaternary logic gates and arithmetic circuits. Microelectron. J. 53, 1177–1193 (2016)

  16. 16.

    D.A. Freitas, K.W. Current, A quaternary logic encoder-decoder circuit design using CMOS, in Proceedings of the International Symposium on Multiple-Valued Logic, (May 1983), pp. 190–195

  17. 17.

    D.A. Freitas, K.W. Current, A CMOS current comparator circuit. Electron. Len. 19(17), 695–697 (1983)

  18. 18.

    K.J. Gan, J.J. Lu, W.K. Yeh, Y.H. Chen, Y.W. Chen, Multiple-valued logic design based on the multiple-peak BiCMOSNDR circuits. Eng. Sci. Technol. Int. J. 19, 888–893 (2016)

  19. 19.

    H. Hashempour, F. Lombardi, Device model for ballistic CNFETs using the first conducting band. IEEE Des. Test Comput. 25(2), 178–186 (2008)

  20. 20.

    A. Heung, H.T. Mouftah, Depletion/enhancement CMOS for a lower power family of three-valued logic circuits. IEEE J. Solid-State Circuit 20(2), 609–616 (1985)

  21. 21.

    S. Kawahito, M. Kameyama, T. Higuchi, H. Yamada, A 32 × 32-bit multiplier using multiple-valued MOS current-mode circuits. IEEE J. Solid-State Cimuits 23(1), 124–132 (1988)

  22. 22.

    P. Keshavarzian, R. Sarikhani, A novel CNTFET-based ternary full adder. Circuits Syst. Signal Process. 33(3), 665–679 (2013)

  23. 23.

    J. Liang, L. Chen, J. Han, F. Lombardi, Design and evaluation of multiple valued logic gates using pseudo N-type carbon nanotube FETs. IEEE Trans. Nanotechnol. 13(4), 695–708 (2014)

  24. 24.

    Y. Lin, J. Appenzeller, J. Knoch, P. Avouris, High-performance carbon nanotube field-effect transistor with tunable polarities. IEEE Trans. Nanotechnol. 4(5), 481–489 (2005)

  25. 25.

    S. Lin, Y.B. Kim, F. Lombardi, The CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans. Nanotechnol. 10(2), 217–225 (2011)

  26. 26.

    M.H. Moaiyeri, R.F. Mirzaee, A. Doostaregan, K. Navi, O. Hashemipour, A universal method for designing low-power carbon nanotube FET-based multiple-valued logic circuits. IET Comput. Digit. Tech. 7(4), 167–181 (2013)

  27. 27.

    M. Mukaidono, Regular ternary logic functions—ternary logic functions suitable for treating ambiguity. IEEE Trans. Comput. 35(2), 179–183 (1986)

  28. 28.

    A. Raychowdhury, K. Roy, Carbon-nanotube-based voltage-mode multiple-valued logic design. IEEE Trans. Nanotechnol. 4(2), 168–179 (2005)

  29. 29.

    D.A. Rich, A survey of multivalued memories. IEEE Trans. Comput. 35(2), 99–106 (1986)

  30. 30.

    E. Roosta, S.A. Hosseini, A novel multiplexer-based quaternary full adder in nanoelectronics. Circuits Syst. Signal Process., (21 Jan. 2019). https://doi.org/10.1007/s00034-019-01039-8

  31. 31.

    M. Shahangian, S.A. Hosseini, S.H. Pishgar Komleh, Design of a multi-digit binary-to-ternary converter based on CNTFETs. Circuits Syst. Signal Process38(6), 2544–2563 (2019)

  32. 32.

    E. Shahrom, S.A. Hosseini, A new low power multiplexer based ternary multiplier using CNTFETs. AEU Int. J. Electron. Commun. 93, 191–207 (2018)

  33. 33.

    K.C. Smith, The prospects for multivalued logic: a technology and applications view. IEEE Trans. Comput. 30(9), 619–634 (1981)

  34. 34.

    Stanford University CNFET model Website. Stanford University, Stanford, CA (2008) (online). http://nano.stanford.edu/model.php?id=23

  35. 35.

    C. Vudadha, P.S. Phaneendra, G. Makkena, V. Sreehari, N.M. Muthukrishnan, M.B. Srinivas, Design of CNFET based ternary comparator using grouping logic, in IEEE Faible Tension Faible Consommation 14, 808 (June 2012)

  36. 36.

    Y. Yasuda, Y. Tokuda, S. Taima, K. Pak, T. Nakamura, A. Yoshida, Realization of quaternary logic circuits by n-channel MOS devices. IEEE J. Solid-State Circuits 21(1), 162–168 (1986)

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Correspondence to Seied Ali Hosseini.

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Hosseini, S.A., Etezadi, S. A Novel Very Low-Complexity Multi-valued Logic Comparator in Nanoelectronics. Circuits Syst Signal Process 39, 223–244 (2020) doi:10.1007/s00034-019-01158-2

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Keywords

  • Multiple-valued logic
  • CNTFET
  • Digital comparator
  • Low complexity