A 79-dB SNR 1.1-mW Fully Integrated Hearing Aid SoC
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For low-power hearing aid device application, a fully integrated optimized hearing aid SoC structure is proposed in this paper. The SoC consists of high-resolution, low-power analog front-end (AFE), time-division-multiplexed power-on-reset circuit, charge pump, digital signal processing (DSP) platform, and Class-D amplifier. A novel peak-statistical algorithm is proposed to track signal amplitude and adjust automatic gain control loop gain precisely. A comparative DWA is applied to break the correlation of in-band tone and sequential selection scheme, which realizes second-order noise shaping and suppresses harmonic effectively. The SoC has been implemented with 0.13 µm CMOS process. By measurement, it shows that the peak signal-to-noise ratio (SNR) of AFE is 82.6 dB and peak SNR of Class-D amplifier is 79.8 dB. Also, three main algorithms of wide dynamic range compression, noise reduction, and feedback cancelation are executed through DSP platform. With 1 V supply voltage, total SoC power is 1.1 mW and core area is 9.3 mm2. Based on our SoC, a hearing aid device prototype is produced that shows its great potential for mass manufacture in the future.
KeywordsHearing aid Low power Analog front-end DSP
This work is supported by the National Natural Science Foundation of China (No. 61704143), Natural Science Foundation of Fujian province (No. 2018J01566), Young- and Middle-aged Teacher Education Research Project of Fujian Province (No. JAT170428), and High-Level Talent Project of Xiamen University of Technology (No. YKJ17019R).
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