500 MHz 90 nm CMOS 2 \(\times \) VDD Digital Output Buffer Immunity to Process and Voltage Variations
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A 2 \(\times \) VDD output buffer in conjunction with a process and voltage (PV) compensation technique is proposed to keep the slew rate (SR) within predefined ranges regardless of PV variations. Temperature variation is not considered as it is found to be relatively less correlated with SR variation for a 90 nm CMOS process or better. All bias voltages in PV variation detectors are generated from bandgap circuits such that variations have been guaranteed by simulation to be less than 4.10%. The proposed design is realized on silicon using a 90 nm CMOS process, where the core area is 0.052 \(\times \) 0.388 mm\(^2\). The data rate is 650/500 MHz given a 1.0/2.0 V supply voltage with a 20 pF load, respectively, by physical measurements. The \(\Delta \) SR improvement is 30.7 and 31.4% for 1 \(\times \) VDD and 2 \(\times \) VDD, respectively, when the proposed PV compensation design is activated.
KeywordsI/O buffer PV variation mixed-voltage tolerant slew rate compensation gate-oxide reliability
This proposed design was partially supported by the Ministry of Science and Technology, Taiwan, under Grant MOST 105-2218-E-110-006-, and the authors would like to express their deepest appreciation to CIC (Chip Implementation Center) in NARL (Nation Applied Research Laboratories), Taiwan, for their knowledgeable assistance in chip fabrication.
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