Circuits, Systems, and Signal Processing

, Volume 38, Issue 2, pp 512–528 | Cite as

Distributed Unique-Size MOS Technique: A Promising Universal Approach Capable of Resolving Circuit Design Bottlenecks of Modern Era

  • Khalil MonfarediEmail author


In this paper, a new universal technique based on the unique-size MOS transistors is proposed to resolve the analog circuit design bottlenecks imposed by nowadays modern technology downscaling. The method called here “distributed MOS (DMOS) technique” not only permits utilizing minimum-size transistors for analog circuit design, but also paves the way to emerging new generation of modern circuits and systems. It is proved that employing the proposed technique helps the optimum performance of the circuit to be preserved, regardless of minimum-size MOS transistors’ narrow channel effect and channel length modulation. This capability is anticipated to be logically maintained for even smaller transistors offered by future technology. The threshold and early voltage variations versus the MOS transistor channel width and length are investigated by numerical analysis of the data achieved from TSMC library for 180-nm technology using Cadence software, and the result uncertainty ascribed to them exhibited an excellent agreement with the initially developed extended MOS model. Higher linearity with lower THD is interestingly achieved for the new approach. The excellent conformity among the simulation and post-layout results verified the efficiency of the proposed design technique in practical circumstances.


Distributed MOS (DMOS) Unique size Universal design approach MOS model Technology downscaling Early voltage variation 


  1. 1.
    L.A. Akers, The inverse-narrow-width effect. IEEE Electron Device Lett. 7, 419–421 (1986)CrossRefGoogle Scholar
  2. 2.
    I.S. Amiri, M. Ghadiry, Introduction on Scaling Issues of Conventional Semiconductors (Springer, Berlin, 2018)CrossRefGoogle Scholar
  3. 3.
    A.J. Annema, B. Nauta, R.V. Langevelde, H. Tuinhout, Analog circuits in ultra-deep-submicron CMOS. IEEE J. Solid-State Circuits 40, 132–143 (2005)CrossRefGoogle Scholar
  4. 4.
    S.J. Azhari, H.F. Baghtash, K. Monfaredi, A novel ultra-high compliance, high output impedance low power very accurate high performance current mirror. Microelectron. J. 42, 432–439 (2011)CrossRefGoogle Scholar
  5. 5.
    C.T. Bowen, System and method for designing a common centroid layout for an integrated circuit, U.S. Patent No. 7,992,117 (2011)Google Scholar
  6. 6.
    A.I.A. Cunha, M.C. Schneider, C. Galup-Montoro, An MOS transistor model for analog circuit design. IEEE J. Solid-State Circuits 33, 1510–1519 (1998)CrossRefGoogle Scholar
  7. 7.
    J. Deveugele, M.S. Steyaert, A 10-bit 250-MS/s binary-weighted current-steering DAC. IEEE J. Solid-State Circuits 41, 320–329 (2006)CrossRefGoogle Scholar
  8. 8.
    C.C. Enz, F. Krummenacher, E.A. Vittoz, An analytical MOS transistor model valid in all regions of operation and dedicated to low-voltage and low-current applications. Analog Integr. Circuits Signal. Process. 8, 83–114 (1995)CrossRefGoogle Scholar
  9. 9.
    C. Fiegna, H. Iwai, T. Wada, M. Saito, E. Sangiorgi, B. Ricco, Scaling the MOS transistor below 0.1/spl mu/m: methodology, device structures, and technology requirements. IEEE Trans. Electron Devices 41, 941–951 (1994)CrossRefGoogle Scholar
  10. 10.
    Y. Frans, S. McLeod, H. Hedayati, M. Elzeftawi, J. Namkoong, W. Lin, J. Im, P. Upadhyaya, K. Chang, A 40-to-64 Gb/s NRZ transmitter with supply-regulated front-end in 16 nm FinFET. IEEE J. Solid-State Circuits 51, 3167–3177 (2016)CrossRefGoogle Scholar
  11. 11.
    P.R. Gray, P.J. Hurst, S.H. Lewis, R.G. Meyer, Analysis and Design of Analog Integrated Circuits, 4th edn. (Wiley, Hoboken, 2008)Google Scholar
  12. 12.
    J.Y. Hasani, Modeling of distributed effects in modern MOS transistors for millimeter wave applications. IEEE Trans. Electron Devices 63, 925–932 (2016)CrossRefGoogle Scholar
  13. 13.
    M. Kumngern, F. Khateb, A low-voltage and low-power multiple-input floating-gate FDCCII, in 12th International Conference on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON), (2015), pp. 1–5Google Scholar
  14. 14.
    Z.H. Liu, C. Hu, J.H. Huang, T.Y. Chan, M.C. Jeng, P.K. Ko, Y.C. Cheng, Threshold voltage model for deep-submicrometer MOSFETs. IEEE Trans. Electron Devices 40, 86–95 (1993)CrossRefGoogle Scholar
  15. 15.
    K. Monfaredi, H.F. Baghtash, S.J. Azhari, A novel ultra-low-power low-voltage femto-ampere current mirror. Circuits Syst. Signal Process. 31, 833–847 (2012)CrossRefGoogle Scholar
  16. 16.
    B. Murmann, P. Nikaeen, D.J. Connelly, R.W. Dutton, Impact of scaling on analog performance and associated modeling needs. IEEE Trans. Electron Devices 53, 2160–2167 (2006)CrossRefGoogle Scholar
  17. 17.
    S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, J. Yamada, 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE J. Solid-State Circuits 30, 847–854 (1995)CrossRefGoogle Scholar
  18. 18.
    S. Nobuyuki, T. Ryuta, I. Takashi, M. Yusuke, Y. Hiroyuki, T. Kazuyoshi, K. Shin’ichiro, Comprehensive study on V th variability in silicon on Thin BOX (SOTB) CMOS with small random-dopant fluctuation: Finding a way to further reduce variation, in IEEE International Electron Devices Meeting (2008), pp. 1–4Google Scholar
  19. 19.
    C. Pacha, B. Martin, K.V. Arnim, R. Brederlow, D. Schmitt-Landsiedel, P. Seegebrecht, J. Berthold, R. Thewes, Impact of STI-induced stress, inverse narrow width effect, and statistical V th variations on leakage currents in 120 nm CMOS, in Proceedings of the 30th European Solid-State Circuits Conference (2004), pp. 397–400Google Scholar
  20. 20.
    S. Park, K.J. Kim, K.H. Ahn, Stabilization technique for multi-inputs voltage sense amplifiers in node sharing converters. World Acad. Sci. Eng. Technol. Int. J. Electr. Comput. Energ., Electron. Commun. Eng. 9, 303–306 (2015)Google Scholar
  21. 21.
    J. Ramirez-Angulo, R.G. Carvajal, A. Torralba, Low supply voltage high-performance CMOS current mirror with low input and output voltage requirements. IEEE Trans. Circuits Syst. II Express Briefs 51, 124–129 (2004)CrossRefGoogle Scholar
  22. 22.
    B. Razavi, Design of Analog CMOS Integrated circuits (2001)Google Scholar
  23. 23.
    B. Razavi, Y. Ran-Hong, K.F. Lee, Impact of distributed gate resistance on the performance of MOS devices. IEEE Trans. Circuits Syst. I: Fundam. Theory Appl. 41, 750–754 (1994)CrossRefGoogle Scholar
  24. 24.
    J. Sarao, Z. Wang, Y. Wu, H. Kwok, An improved regulated cascode current mirror. Solid-State Electron. 46, 307–312 (2002)CrossRefGoogle Scholar
  25. 25.
    B.J. Sheu, D.L. Scharfetter, P.K. Ko, M.C. Jeng, BSIM: Berkeley short-channel IGFET model for MOS transistors. IEEE J. Solid-State Circuits 22, 558–566 (1987)CrossRefGoogle Scholar
  26. 26.
    N. Sugii, R. Tsuchiya, T. Ishigaki, Y. Morita, H. Yoshimoto, S. Kimura, Local V th variability and scalability in Silicon-on-Thin-BOX (SOTB) CMOS with small random-dopant fluctuation. IEEE Trans. Electron Devices 57, 835–845 (2010)CrossRefGoogle Scholar
  27. 27.
    P. Upadhyaya, J. Savoj, F.T. An, A. Bekele, A. Jose, B. Xu, D. Wu, D. Turker, H. Aslanzadeh, H. Hedayati, J. Im, 3.3 A 0.5-to-32.75 Gb/s flexible-reach wireline transceiver in 20 nm CMOS, in IEEE International Solid-State Circuits Conference (2015), pp. 1–3Google Scholar
  28. 28.
    P.P. Wang, Device characteristics of short-channel and narrow-width MOSFET’s. IEEE Trans. Electron Devices 25, 779–786 (1978)CrossRefGoogle Scholar
  29. 29.
    X. Zhou, K.Y. Lim, D. Lim, A simple and unambiguous definition of threshold voltage and its implications in deep-submicron MOS device modeling. IEEE Trans. Electron Devices 46, 807–809 (1999)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electrical and Electronic Engineering, Faculty of EngineeringAzarbaijan Shahid Madani UniversityTabrizIran

Personalised recommendations