Circuits, Systems, and Signal Processing

, Volume 37, Issue 9, pp 4162–4180 | Cite as

Designing Efficient Two-Level Reverse Converters for Moduli Set \(\{2^{2n+1}-1,2^{2n},2^{n}-1\}\)

  • Navid SalehiTabrizi
  • Shiva TaghipourEivaziEmail author
Short Paper


Residue number system is a non-weighted system in which some arithmetic operations are performed parallelly. A factor that affects the system’s performance is the complexity of converters, as the complexity of reverse converter should not discomfit the earned speed of parallelly performing arithmetic unit. In this paper, two efficient reverse converters are proposed for moduli set \(\{2^{2n+1}-1,2^{2n},2^{n}-1\}\) by using two-level method and mixed-radix conversion algorithm. Both unit gate model and simulation are used to have an efficient comparison. The novel converters and the recently presented reverse converters with similar dynamic range were implemented in Hardware Description Language on Xilinx 13.1 FPGA simulator. Area and delay of each converter were measured for various dynamic range up to 256 bits. As the results indicated, the novel proposed area-efficient converter and delay-efficient converter indicate an improvement about 8 and 14%, respectively, in terms of time complexity comparing to the recently presented design.


Residue number system Mixed-radix conversion Computer arithmetic Parallel computation VLSI architectures 


  1. 1.
    A. Ammar, A.A. Kabbany, M. Youssef, A. Emam, A secure image coding using residue number systems. in Proceedings of the 18th National Radio Science Conference (2001)
  2. 2.
    J.C. Bajard, L. Imbert, A full RNS implementation of RSA. IEEE Trans. Comput. 53(6), 769–774 (2004)CrossRefGoogle Scholar
  3. 3.
    E.K. Bankas, K.A. Gbolagade, New MRC adder-based reverse converter for the moduli set \(\{2^{n},2^{2n+1}-1,2^{2n+2}-1\}\). Comput. J. 58(7), 1566–1572 (2015)CrossRefGoogle Scholar
  4. 4.
    M. Bhardwaj, T. Srikanthan, C.T. Clarke, A reverse converter for the 4-moduli superset \(\{2^{n}-1,2^{n},2^{n}+1,2^{n+1}+1\}\). in Proceedings of the 14th IEEE Symposium Computer Arithmetic (Cat. No. 99CB36336), (1999).
  5. 5.
    G. Campobello, A. Leonardi, S. Palazzo, Improving energy saving and reliability in wireless sensor networks using a simple CRT based packet-forwarding solution. IEEE/ACM Trans. Netw. 20(1), 191–205 (2012)CrossRefGoogle Scholar
  6. 6.
    B. Cao, C.H. Chang, T. Srikanthan, A residue-to-binary converter for a new five-moduli set. IEEE Trans. Circuits Syst. I 54(5), 1041–1049 (2007)MathSciNetCrossRefzbMATHGoogle Scholar
  7. 7.
    C. Chang, A. Molahosseini, A. Zarandi, T. Tay, Residue number systems: a new paradigm to datapath optimization for low-power and high-performance digital signal processing applications. IEEE Circuits Syst. Mag. 15(4), 26–44 (2015)CrossRefGoogle Scholar
  8. 8.
    R. Conway, J. Nelson, Improved RNS FIR filter architectures. IEEE Trans. Circuits Syst. II, Exp. Briefs 51(1), 26–28 (2004)CrossRefGoogle Scholar
  9. 9.
    K.M. Ibrahim, S.N. Saloum, An efficient residue to binary converter design. IEEE Trans. Circuits Syst. 35(9), 11561 158 (1988)CrossRefzbMATHGoogle Scholar
  10. 10.
    S. Lin, M. Sheu, C. Wang, Efficient VLSI design of residue-to-binary converter for the moduli set \((2^{n},2^{n+1}-1,2^{n}-1)\). IEICE Trans. Inf. Syst. E 91–D(7), 2058–2060 (2008)CrossRefGoogle Scholar
  11. 11.
    P.V. Mohan, RNS to binary converter for a new three moduli set \(\{2^{n+1}-1,2^{n},2^{n}-1\}\). IEEE Trans. Circuits Syst. II 54(9), 775–779 (2007)CrossRefGoogle Scholar
  12. 12.
    K. Navi, M. Esmaeildoust, A.S. Molahosseini, A general reverse converter architecture with low complexity and high performance. IEICE Trans. Inf. Syst. E 94–D(2), 264–273 (2011)CrossRefGoogle Scholar
  13. 13.
    K. Navi, A.S. Molahosseini, M. Esmaeildoust, How to teach residue number system to computer scientists and engineers. IEEE Trans. Educ. 71(2), 226–272 (2011)Google Scholar
  14. 14.
    M.R. Noorimehr, M. Hosseinzadeh, R. Farshidi, High speed residue to binary converter for the new four-moduli set \(\{2^{2n},2^{n}+1,2^{n/2}+1,2^{n/2}-1\}\). Arab J. Sci. Eng. 39(4), 2887–2893 (2014)MathSciNetCrossRefzbMATHGoogle Scholar
  15. 15.
    M.R. Noorimehr, M. Hosseinzadeh, K. Navi, Efficient reverse converters for 4-moduli sets \(\{2^{2n-1}-1,2^{n},2^{n}+1,2^{n}-1\}\) and \(\{2^{2n-1}-1,2^{2n-1},2^{n}+1,2^{n}-1\}\) based on CRTs algorithm. Circuits Syst. Signal Process. 33(10), 3145–3163 (2014)CrossRefzbMATHGoogle Scholar
  16. 16.
    A. Omondi, B. Premkumar, Residue Number System Theory and Implementation (Imperial College Press, London, 2000)zbMATHGoogle Scholar
  17. 17.
    R. Schneiderman, DSPs evolving in consumer electronics applications. IEEE Signal Process. Mag. 27(3), 6–10 (2010)CrossRefGoogle Scholar
  18. 18.
    L. Sousa, S. Antao, R. Chaves, On the design of RNS reverse converters for the four-moduli set \(\{2^{n}+1,2^{n}-1,2^{n},2^{n+1}+1\}\). IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(10), 1945–1949 (2013)CrossRefGoogle Scholar
  19. 19.
    N.S. Szabo, R.I. Tanaka, Residue Arithmetic and its Applications to Computer Technology (McGraw-Hill, New York, 1967)zbMATHGoogle Scholar
  20. 20.
    S. TaghipourEivazi, M. Hosseinzadeh, A. HabibiZadNovin, Efficient RNS converter via two-part RNS. J. Circuits Syst. Comput. 24(1), 1550016 (2015)CrossRefGoogle Scholar
  21. 21.
    Y. Wang, X. Song, M. Aboulhamid, H. Shen, Adder based residue to binary number converters for \((2^{n}-1,2^{n},2^{n}+1)\). IEEE Trans. Signal Process. 50(7), 1772–1779 (2002)MathSciNetCrossRefzbMATHGoogle Scholar
  22. 22.
    R. Zimmermann, Efficient VLSI implementation of modulo \((2^{n}\pm 1)\) addition and multiplication. in Proceedings of the 18th IEEE International Symposium Computer Arithmetic, (1999).

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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Computer Engineering, Tabriz BranchIslamic Azad UniversityTabrizIran

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