Circuits, Systems, and Signal Processing

, Volume 37, Issue 9, pp 3888–3902 | Cite as

Semiempirical Model for IC Interconnects Considering the Coupling Between the Signal Trace and the Ground Plane

  • Mónico Linares-ArandaEmail author
  • Oscar González-Díaz
  • Diego M. Cortés-Hernández
  • Reydezel Torres-Torres


A semiempirical, piecewise-defined, and physical model for integrated circuit interconnects is presented. The proposed model accurately represents the corresponding frequency-dependent resistance, and self- and mutual inductances while also accounting for the eddy currents induced in the ground metal layer. For the model implementation, different frequency regions where the resistance, and the self- and mutual inductances exhibit different trends due to the variation in the effective area where the current is flowing are identified, as well as the corresponding transitional frequencies. Experimental results performed to on-chip test structures fabricated on an RF-CMOS technology are used to validate the proposed model up to 40 GHz.


Series resistance Mutual inductance On-chip interconnects Ground plane Integrated circuits VLSI 


  1. 1.
    M.S. Alavi, J. Mehta, R.B. Staszewski, Radio-Frequency Digital-to-Analog Converters: Implementation in Nanoscale CMOS (Academic Press, London, 2017)Google Scholar
  2. 2.
    B. Bhat, S.K. Koul, Stripline-Like Transmission Lines for Microwave Integrated Circuit (New Age International, New Delhi, 1989)Google Scholar
  3. 3.
    T. Brozek, Micro- and Nanoelectronics: Emerging Device Challenges and Solutions (CRC Press, Toronto, 2015)Google Scholar
  4. 4.
    J. Cano, J. Flich, J. Duato, M. Coppola, R. Locatelli, Efficient routing implementation in complex systems-on-chip, in Proceedings of the Fifth ACM/IEEE International Symposium, pp. 1–8 (2011)Google Scholar
  5. 5.
    M.H. Chowdhury, Y.I. Ismail, C.V. Kashyap, B.L. Krauter, Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance, in IEEE International Symposium on Circuits and Systems, pp. 197–200 (2002)Google Scholar
  6. 6.
    D.M. Cortés-Hernández, R. Torres-Torres, O. González-Díaz, M. Linares-Aranda, Experimental characterization of frequency-dependent series resistance and inductance for ground shielded on-chip interconnects. IEEE Trans. Electromagn. Compat. 56(6), 1567–1575 (2014)CrossRefGoogle Scholar
  7. 7.
    D.M. Cortés-Hernández, R. Torres-Torres, M. Linares-Aranda, O. González-Díaz, Piecewise physical modeling of series resistance and inductance of on-chip interconnects. Solid State Electron. 120, 1–5 (2016)CrossRefGoogle Scholar
  8. 8.
    A.R. Djordjevic, M. Stojilovic, T.K. Sarkar, Closed-form formulas for frequency-dependent per-unit-length inductance and resistance of microstrip transmission lines that provide causal response. IEEE Trans. Electromagn. Compat. 56(6), 1604–1612 (2014)CrossRefGoogle Scholar
  9. 9.
    S.H. Hall, H.L. Heck, Advanced Signal Integrity for High-Speed Digital Designs (Wiley, Hoboken, 2009)CrossRefGoogle Scholar
  10. 10.
    J.P. Jansson, P. Keränen, J. Kostamovaara, A. Baschirotto, CMOS technology scaling advantages in time domain signal processing. IEEE international instrumentation and measurement technology conference (I2MTC), pp. 1–5 (2017)Google Scholar
  11. 11.
    V.K. Khanna, Integrated Nanoelectronics: Nanoscale CMOS (Post-CMOS and Allied Nanotechnologies, India, 2016)CrossRefGoogle Scholar
  12. 12.
    D.W. Kim, C. Li, P.L.G. Qiang, Signal integrity and crosstalk analysis of the transmission lines on SOI substrate for high-speed up to 50 GHz, in IEEE 18th Electronics Packaging Technology Conference (EPTC), pp. 633–637 (2016)Google Scholar
  13. 13.
    H. Kim, D. Kim, Y. Eo, Experimental via characterization for the signal integrity verification of discontinuous interconnect line, in International SoC Design Conference, Seoul, pp. 213–216 (2010)Google Scholar
  14. 14.
    J.H. Kim, D. Oh, W. Kim, Accurate characterization of broadband multiconductor transmission lines for high-speed digital systems. IEEE Trans. Adv. Packag. 33(4), 857–867 (2010)CrossRefGoogle Scholar
  15. 15.
    P. Majumdar, A.K. Verma, Comparison of characteristics of transmission lines using different EM simulators, in Fourth International Conference on Advanced Computing & Communication Technologies, pp. 1–7 (2014)Google Scholar
  16. 16.
    A.M. Mangan, S.P. Voinigescu, Yang Ming-Ta, M. Tazlauanu, De-embedding transmission line measurements for accurate modeling of IC designs. IEEE Trans. Electron Devices 53(2), 235–241 (2006)CrossRefGoogle Scholar
  17. 17.
    L. Moquillon, J.M. Fournier, P. Benech, T. Quemerais, 65-, 45-, and 32-nm Aluminium and copper transmission-line model at millimeter-wave frequencies. IEEE Trans. Microw. Theory Tech. 58(9), 2426–2433 (2010)CrossRefGoogle Scholar
  18. 18.
    B. Nauwelaers, K. Maex, H. Ymeri, New closed-form formula for frequency-dependent resistance and inductance of IC interconnects on silicon substrate. J. Micromech. Microeng. 11(3), 283–286 (2001)CrossRefzbMATHGoogle Scholar
  19. 19.
    I. Ndip, S. Guttowski, B. Curran, H. Reichl, A methodology for combined modeling of skin, proximity, edge, and surface roughness effects. IEEE Trans. Microw. Theory Tech. 58(9), 2448–2455 (2010)CrossRefGoogle Scholar
  20. 20.
    D. Pasquet, P. Descamps, D. Lesenechal, L. Nguyen-Tran, E. Bourdel, S. Quintanel, Modelling of an inductor on SiGe: from the measurement to the equivalent scheme, in Microwaves, Radar and Remote Sensing Symposium, pp. 59–64 (2011)Google Scholar
  21. 21.
    M. Patil et al., Chip-package-board co-design for complex system-on-chip (SoC), in 19th Topical Meeting on Electrical Performance of Electronic Packaging and Systems, pp. 273–276 (2010)Google Scholar
  22. 22.
    J.C. Rautio, V. Demir, Microstrip conductor loss models for electromagnetic analysis. IEEE Trans. Microw. Theory Tech. 51(3), 915–921 (2003)CrossRefGoogle Scholar
  23. 23.
    F. Schnieder, W. Heinrich, Model of thin-film microstrip line for circuit design. IEEE Trans. Microw. Theory Tech. 49(1), 104–110 (2001)CrossRefGoogle Scholar
  24. 24.
    L.N. Tran, D. Pasquet, E. Bourdel, S. Quintanel, CAD-oriented model of a coplanar line on a silicon substrate including eddy-current effects and skin effect. IEEE Trans. Microw. Theory Tech. 56(3), 663–670 (2008)CrossRefGoogle Scholar
  25. 25.
    M.S. Ullah, M.H. Chowdhury, Analytical models of high-speed RLC interconnect delay for complex and real poles. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(6), 1831–1841 (2017)CrossRefGoogle Scholar
  26. 26.
    D.F. Williams, R.B. Marks, Accurate transmission line characterization. IEEE Microw. Guided Wave Lett. 3(8), 247–249 (1993)CrossRefGoogle Scholar
  27. 27.
    L. Zerioul, E. Bourdel, M. Ariaudo, Skin effect modeling in time domain for RF network on chip, in 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), pp. 721–724 (2012)Google Scholar
  28. 28.
    L. Zerioul, M. Ariaudo, E. Bourdel, RF transceiver and transmission line behavioral modeling in VHDL-AMS for wired RFNoC. Analog Integr. Circuits Signal Process. 92(1), 103–114 (2017)CrossRefGoogle Scholar
  29. 29.
    J. Zhang et al., Causal RLGC(\(f)\) models for transmission lines from measured \(S\)-parameters. IEEE Trans. Electromagn. Compat. 52(1), 189–198 (2010)CrossRefGoogle Scholar

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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of ElectronicsInstituto Nacional de Astrofísica, Óptica y Electrónica (INAOE)Santa. María TonantzintlaMéxico
  2. 2.Board Development, Intel Tecnología de MéxicoZapopanMéxico

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