Circuits, Systems, and Signal Processing

, Volume 37, Issue 9, pp 4049–4064 | Cite as

Geometric Programming-Based Power Optimization and Design Automation for a Digitally Controlled Pulse Width Modulator

  • P. Rajeswari
  • G. Shekar
  • S. Devi
  • A. PurushothamanEmail author
Short Paper


This paper proposes a tool for the synthesis of the design and optimization of digitally controlled pulse width modulator (PWM). There are three phases for the proposed tool. In the first phase, an accurate transistor level model for 90 nm fabrication technology is generated using MATLAB curve-fitting tool box (Dunbar in Am J Phys 24(6):464–464, 1956) and Cadence Spectre Circuit Simulator, which successfully replicates the transistor performance of Cadence 90 nm fabrication technology. In the second phase, the PWM specification is optimally decomposed among its subcomponents. The optimized design of subcomponents is accomplished via Geometric programming in the third phase. A practical design example in Cadence 90 nm fabrication technology is presented to substantiate the suggested methodology for unified design automation and power optimization.


Pulse width modulator Geometric programming Interior point method Design automation 


  1. 1.
    B.A.A. Antao, A.J. Brodersen, Techniques for synthesis of analog integrated circuits. IEEE Des. Test Comput. 9(1), 8–18 (1992)CrossRefGoogle Scholar
  2. 2.
    M. Bhanja, B.N. Ray, Synthesis procedure of configurable building block based linear and nonlinear analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(12), 1940–1953 (2017)CrossRefGoogle Scholar
  3. 3.
    S.P. Boyd, S.-J. Kim, D.D. Patil, M.A. Horowitz, 2005. Digital Circuit Optimization via Geometric Programming. pp. 899–932 (2006)Google Scholar
  4. 4.
    L.R. Carley, R.A. Rutenbar, How to automate analog IC designs. IEEE Spectr. 25(8), 26–30 (1988)CrossRefGoogle Scholar
  5. 5.
    D. Chen, T. Aoki, N. Homma, T. Terasaki, T. Higuchi, Graph-based evolutionary design of arithmetic circuits. IEEE Trans. Evol. Comput. 6(1), 86–100 (2002)CrossRefGoogle Scholar
  6. 6.
    Y.-T. Chien, D. Chen, J.-H. Lou, G.-K. Ma, R.A. Rutenbar, T. Mukherjee, Designer-driven topology optimization for pipelined analog to digital converters, in Design, Automation and Test in Europe, pp. 279–280 (2005)Google Scholar
  7. 7.
    M. Conti et al., Layout-based statistical modeling for the prediction of the matching properties of MOS transistors. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. 49(5), 680–685 (2002)CrossRefGoogle Scholar
  8. 8.
    A. DeHon, K.K. Likharev, Hybrid CMOS/nanoelectronic digital circuits: devices, architectures, and design automation, in IEEE/ACM International Conference on Computer-Aided Design, pp. 375–382 (2005)Google Scholar
  9. 9.
    L.E. Dunbar, Curve fitting. Am. J. Phys. 24(6), 464–464 (1956)CrossRefGoogle Scholar
  10. 10.
    A. Garimella, L. M. Kalyani-Garimella, R. Romero, J. Ramirez-Angulo, R. G. Carvajal, A. J. Lopez-Martin, Versatile multidecade CMOS voltage controlled oscillator with accurate amplitude and PWM control, in 50th Midwest Symposium on Circuits and Systems, pp. 45–48 (2007)Google Scholar
  11. 11.
    M.D. Hershenson, S.P. Boyd, T.H. Lee, Optimal design of a CMOS op-amp via geometric programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1), 1–21 (2001)CrossRefGoogle Scholar
  12. 12.
    L. Hernandez, E. Prefasi, S. Paton, P. Rombouts, Analysis of VCO based noise shaping ADCs linearized by PWM modulation, in 19th IEEE International Conference on Electronics, Circuits, and Systems, pp. 352–355 (2012)Google Scholar
  13. 13.
    M. Horowitz, E. Alon, D. Patil, S. Naffziger, R. Kumar, K. Bernstein, Scaling, power, and the future of CMOS, in IEEE International Meeting on Electron Devices Meeting, pp. 7–15 (2005)Google Scholar
  14. 14.
    C.P. Huang, J.M. Lin, Y.T. Shyu, S.J. Chang, A. Systematic, Design methodology of asynchronous SAR ADCs. IEEE Trans. Very Large Scale Integr. VLSI Syst. 24(5), 1835–1848 (2016)CrossRefGoogle Scholar
  15. 15.
    W. Jung, Y. Mortazavi, B.L. Evans, A. Hassibi, An all-digital PWM-based Delta-Sigma ADC with an inherently matched multi-bit quantizer, in 26th Custom Integrated Circuits Conference, pp. 1–4 (2014)Google Scholar
  16. 16.
    K. Jeppson, A learning tool MOSFET model: A stepping-stone from the square-law model to BSIM4, in 23rd International Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 39–44 (2013)Google Scholar
  17. 17.
    S.J. Kim, S.P. Boyd, S. Yun et al., A heuristic for optimizing stochastic activity networks with applications to statistical digital circuit sizing. Optim. Eng. 8(4), 397–430 (2007)MathSciNetCrossRefzbMATHGoogle Scholar
  18. 18.
    J. Kim et al., Multilevel power optimization of pipelined A/D converters. IEEE Trans. Very Large Scale Integr. 19(2), 832–845 (2011)CrossRefGoogle Scholar
  19. 19.
    N. Nedic, V. Stojanovic, V. Djordjevic, Optimal control of hydraulically driven parallel robot platform based on firefly algorithm. Nonlinear Dyn. 82(3), 1457–1473 (2015)MathSciNetCrossRefGoogle Scholar
  20. 20.
    E.S. Ochotta, R.A. Rutenbar, L.R. Carley, Synthesis of high-performance analog circuits in ASTRX/OBLX. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(3), 273–294 (1996)CrossRefGoogle Scholar
  21. 21.
    F. Padilla, A. Torres, et al., Evolvable metaheuristics on circuit design, in Advances in Analog Circuits (2014) (chapter 16) Google Scholar
  22. 22.
    D. Patil, S. Yun, S.J. Kim, A. Cheung, M. Horowitz, S. Boyd, A new method for design of robust digital circuits. in 6th International Symposium on Quality Electronic Design, pp. 676–681 (2005)Google Scholar
  23. 23.
    M.J.M. Pelgrom et al., Matching properties of MOS transistors. IEEE J. Solid State Circuits 24(5), 1433–1439 (1989)CrossRefGoogle Scholar
  24. 24.
    A. Purushothaman, C.D. Parikh, A new delay model and geometric programming-based design automation for latched comparators. Circuits Syst. Signal Process. 34(9), 2749–2764 (2015)CrossRefGoogle Scholar
  25. 25.
    A. Purushothaman, MINLP based power optimization for pipelined ADC, in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Pittsburgh, pp. 508–511 (2016)Google Scholar
  26. 26.
    S. Rao, B. Young, A. Elshazly, W. Yin, N. Sasidhar, P.K. Hanumolu, A 71dB SFDR open loop VCO-based ADC using 2-level PWM modulation, in 24th Symposium on VLSI Circuits-Digest of Technical Papers, pp. 270–271 (2011)Google Scholar
  27. 27.
    V. Stojanovic, N. Nedic, A nature inspired parameter tuning approach to cascade control for hydraulically driven parallel robot platform. J. Optim. Theory Appl. 168(1), 332–347 (2016)MathSciNetCrossRefzbMATHGoogle Scholar
  28. 28.
    C. Toumazou, C.A. Makris, Analog IC design automation. I. Automated circuit generation: new concepts and methods. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2), 218–238 (1995)CrossRefGoogle Scholar
  29. 29.
    I. Vaisband, M. Azhar, E.G. Friedman, S. Köse, Digitally controlled pulse width modulator for on-chip power management. IEEE Trans. Very Large Scale Integr. VLSI Syst. 22(12), 2527–2534 (2014)CrossRefGoogle Scholar
  30. 30.
    J. Yuan, N. Farhat, J. Van der Spiegel, GBOPCAD: a synthesis tool for high-performance gain-boosted opamp design. IEEE Trans. Circuits Syst. I Regul. Pap. 52(8), 1535–1544 (2005)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2017

Authors and Affiliations

  • P. Rajeswari
    • 1
  • G. Shekar
    • 1
  • S. Devi
    • 1
  • A. Purushothaman
    • 1
    Email author
  1. 1.Department of Electronics and Communication Engineering, Amrita School of EngineeringAmrita Vishwa VidyapeethamAmritapuriIndia

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