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Repairing VLSI/WSI redundant memories with minimum cost

Abstract

A new approach to repair memory chips with redundancy is proposed. This approach is based on the minimization of the repair cost. Algorithms for cost driven repair are presented. The algorithms can be executed either on-line (concurrently with the testing of the memory), or off-line (at completion of testing).

Analytical expressions for the repair cost under both circumstances are given. The presented algorithms are also perfect in the sense that they can correctly diagnose a repairable/unrepairable memory and find the optimal repair-solution.

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References

  1. [1]

    Benevit, C.A.et al., A 256k dynamic random access memory,IEEE J. of Solid-State Circuits, SbdSC-17: 5 (1982), 857–862.

  2. [2]

    Cenker, R.P.et al., A fault tolerant 64k dynamic random access memory,IEEE Trans. on Electron Devices,ED-26:6(1979), 853–860.

  3. [3]

    Okajima, Yet al., 64kb ECL RAM with Redundancy,Proc. IEEE ISSCC, 48–49, 1985.

  4. [4]

    Evans, R.C., Testing Repairable RAMS and Mostly Good Memories,Proc. IEEE ITC, 49–55, 1981.

  5. [5]

    Smith, R.T.et al., Laser programmable redundancy and yield improvement in a 64k DRAM,IEEE J. of Solid-State Circuits,SC-16: 5(1981), 506–514.

  6. [6]

    Wey, C-L and Lombardi, F., On the repair of redundant RAMS,IEEE Trans. on CAD, CAD-6: 2(1987).

  7. [7]

    Kuo, S-Y and W.K. Fuchs, Efficient Spare Allocation in Reconfigurable Arrays,Proc. ACM/IEEE DAC, 385–390, 1986.

  8. [8]

    Dahbura, A.T. and Haddad, R.W., Increasing the Throughput of the Testing and Repair of RAMs with Redundancy,AT&T Bell Labs. Internal Report, Murray Hill, 1986; also in Proc. IEEE ICCAD, Santa Clara, 1987.

  9. [9]

    Huang, K.W. and Lombardi, F., Approaches for the Repair of VLSI/WSI RRAMs by Row/Column Deletion, Proc. Fault Tolerant Computing Symposium, Tokyo, June 1988.

  10. [10]

    Day, J.R., A fault-driven comprehensive redundancy algorithm for repair of dynamic RAMs,IEEE Design and Test of Computers,2:3(1985), 33–44.

  11. [11]

    Fizgerald, B.F. and Thoma, E.P., Circuit implementation of fusible redundant addresses of RAMs for productivity enhancement,IBM J. Res. Develop.,24(1980), 291–298.

  12. [12]

    Stapper, C.H., On a composite model to the IC yield problem,IEEE J. of Solid State Circuits,SC-10(1975).

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Author information

Correspondence to Weikang Huang.

Additional information

This research is supported in part by grants from AT&T and NATO.

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Huang, W., Lombardi, F. Repairing VLSI/WSI redundant memories with minimum cost. J. of Compt. Sci. & Technol. 5, 187–196 (1990). https://doi.org/10.1007/BF02943424

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Keywords

  • Repair Process
  • Repair Cost
  • Dynamic Random Access Memory
  • Memory Array
  • Faulty Cell