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Repairing VLSI/WSI redundant memories with minimum cost


A new approach to repair memory chips with redundancy is proposed. This approach is based on the minimization of the repair cost. Algorithms for cost driven repair are presented. The algorithms can be executed either on-line (concurrently with the testing of the memory), or off-line (at completion of testing).

Analytical expressions for the repair cost under both circumstances are given. The presented algorithms are also perfect in the sense that they can correctly diagnose a repairable/unrepairable memory and find the optimal repair-solution.

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Author information

Correspondence to Weikang Huang.

Additional information

This research is supported in part by grants from AT&T and NATO.

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Huang, W., Lombardi, F. Repairing VLSI/WSI redundant memories with minimum cost. J. of Compt. Sci. & Technol. 5, 187–196 (1990).

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  • Repair Process
  • Repair Cost
  • Dynamic Random Access Memory
  • Memory Array
  • Faulty Cell