Advertisement

Springer Nature is making SARS-CoV-2 and COVID-19 research free. View research | View latest news | Sign up for updates

Robust tests for parity trees

  • 21 Accesses

  • 2 Citations

Abstract

Linear logic circuits are used extensively in digital computing and signal processing systems. They are constructed as regular arrays (for example as cascade or tree circuits), employing linear gates such as Exclusive OR (EOR) and Exclusive NOR (ENOR) gates. Earlier studies on fault diagnosis in linear logic circuits were based on the classical fault model of line stuck-at faults. Transistor stuck-open (SOP) and stuck-on (SON) faults in linear circuits were studied recently, but the effect of signal transients due to circuit delays and time skews in input changes were not considered in the derivation of test sequences. These latter factors are known to cause invalidation of two pattern tests for stuck-open faults. In this article we consider the problem of generating robust tests for linear logic circuits. These tests are not affected by circuit transients caused by delays. A major finding in this paper is that, if the test invalidation problem is redressed by introducing robust tests, the test length becomes a linear function of the depth of the circuit as opposed to the constant number of tests derived in previous studies, by neglecting circuit transients. A lower bound on minimum number of distinct test patterns needed for a tree of EOR gates of depthd is derived. This number depends on the specific implementation of the gate. Robust test-generation procedures are proposed for both single and multiple fault models and their optimalities are argued. Given that every gate in a parity tree is robustly testable, a test sequence that can test for all faults in the circuit, regardless of the nature of gate implementation, is calleduniversal robust test sequence for a parity tree. Finally we propose an optimal universal robust test sequence.

This is a preview of subscription content, log in to check access.

References

  1. 1.

    G. Strang, “Linear algebra and its applications,” 2nd ed. New York: Academic Press, 1980.

  2. 2.

    S.M. Reddy, “Easily testable realizations for logic functions,”IEEE Trans. Comput. vol. C-21, pp. 1183–1189, November 1972.

  3. 3.

    K.K. Saluja and M. Karpovsky, “Testing computer hardware through data compression in space and time,”Proc. Inter. Test Conf., pp. 83–88, October 1983.

  4. 4.

    T.R.N. Rao, “Error coding for arithmetic processors,” New York: Academic Press, 1974.

  5. 5.

    D.C. Bossen, D.L. Ostapko, and A.M. Patel, “Optimum test patterns for parity networks,”Proc. IFIPS Fall Joint Comput. Conf., pp. 63–68, November 1970.

  6. 6.

    M.A. Breuer, “Generation of fault tests for linear logic networks,”IEEE Trans. Comput. vol. C-21, pp. 79–83, January 1972.

  7. 7.

    S.C. Seth and K.L. Kodandapani, “Diagnosis of faults in linear tree networks,”IEEE Trans. Comput., vol. C-26, pp. pp. 29–33, January 1977.

  8. 8.

    J. Khakbaz, “Self-testing embedded parity trees,”Proc. 12th Fault-Tolerant Comput. Symp., pp. 109–116, June 1982.

  9. 9.

    J. Khakbaz and E.J. McCluskey, “Self-testing embedded parity checkers,”IEEE Trans. Comput. vol. C-33, pp. 753–756, August 1984.

  10. 10.

    S.M. Reddy, K.K. Saluja, and M. Karpovsky, “A data compression technique for built-in self-test,”Proc. of 15th Fault-Tolerant Comput. Symp., pp. 294–299, June 1985.

  11. 11.

    S. Mourad, J.L. Aughas, and E.J. McCluskey, “Stuck-at fault detection in parity trees,”Proc. Fault-Tolerant Syst. Diag. Conf., Brno, Czechoslovakia, pp. 142–147, June 1986.

  12. 12.

    E.J. McCluskey, “Built-in verification test,” Center for Reliable Computing Systems Laboratory, Stanford University, Stanford, California, July 1982.

  13. 13.

    S.M. Reddy, M.K. Reddy, and J.G. Kuhl, “On testable designs for CMOS logic circuits,”Proc. Inter. Test Conf., pp. 435–445, October 1983.

  14. 14.

    S.K. Jain and V.D. Agarwal, “Test generation for MOS circuits using D-algorithm,”20th Design Automation Conf., pp. 64–70, June 1983.

  15. 15.

    S.M. Reddy et al., “Robust tests for stuck-open faults in CMOS combinational logic circuit,”Proc. 14th Fault-Tolerant Comput. Symp., pp. 44–49, June 1984.

  16. 16.

    S. Kundu, “Design of testable CMOS circuits and codes for TSC systems,” Ph.D. Thesis, Department of Electrical and Computer Engineering, University of Iowa, Iowa City, Iowa, May 1988.

  17. 17.

    N.K. Jha and J.A. Abraham, “Testable CMOS logic circuits under dynamic behaviour,”Inter. Conf. Comput. Aided Design, pp. 131–133, November 1984.

Download references

Author information

Rights and permissions

Reprints and Permissions

About this article

Cite this article

Kundu, S., Reddy, S.M. Robust tests for parity trees. J Electron Test 1, 191–200 (1990). https://doi.org/10.1007/BF00938682

Download citation

Key words

  • linear gates
  • parity trees
  • robust tests
  • test length
  • URTS