Testing large VLSI circuits is a difficult and challenging problem for designers. Large unstructured circuits are often impossible to test. The number of test vectors also tend to be large and difficult to generate using automated tools for testing. In this paper, we have investigated the testing of systolic arrays built from a finite ring cell that has been proposed recently for digital signal processing functions. The cell has been shown to allow encoding, decoding and general inner product type computations for residue number system applications, with considerable advantages over equivalent binary implementation. As a further feature, we show, in this paper, that an array of such cells is remarkably easy to test for stuck-at faults. Generating test vectors for these arrays is also straightforward.
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Jullien, G.A., Bandyopadhyay, S., Miller, W.C. et al. A low-overhead scheme for testing a bit-level finite ring systolic array. J VLSI Sign Process Syst Sign Image Video Technol 2, 131–137 (1990). https://doi.org/10.1007/BF00935210
- Digital Signal Processing
- Data Path
- Test Vector
- Systolic Array
- Residue Number System