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Efficient microcoded processor design for fixed rate DFT and FFT

Abstract

Many Fourier transform applications have to operate at fixed sample rates in the low to medium range, especially in signal processing systems. Hence, in order to arrive at efficient implementations, hardware-sharing is required as in microcoded architectures. In this paper, very efficient application-specific realizations spanning a wide throughput range are proposed for both DFT and FFT algorithms. Novel single-cycle address computations are presented for the FFT to obtain these results. Trade-offs between the architectural alternatives are provided too. These designs have been used as test-vehicles for the architectural strategy in an automated synthesis tool-box tuned towards signal processing applications.

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This research has been sponsored in part within the context of the ESPRIT97 project by the EC and the industrial partners Philips, Siemens, BTMC/Alcatel and Silvar/Lisco.

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Catthoor, F., Lanneer, D. & De Man, H. Efficient microcoded processor design for fixed rate DFT and FFT. J VLSI Sign Process Syst Sign Image Video Technol 1, 287–306 (1990). https://doi.org/10.1007/BF00929923

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Keywords

  • Idle Cycle
  • Pitch Extraction
  • IEEE Custom Integrate Circuit
  • Background Memory
  • Butterfly Operation