Adaptive sample rate filtering has been shown to be an efficient and effective method of removing narrowband interference from broadband communication signals. The expression for the gradient for adaptive sample rate filtering is expressed in terms of the traditional adaptive filter gradient. Adaptive algorithms frequently use divide and square operations. Rather than implementing a generic multiplier in the adaptive section for the adaptive sample rate notch filter, we have developed a technique of optimizing an implementation of the squarer. In the sequential reciprocal circuit presented, we show how a numerator (scaling) can be easily incorporated into its design to achieve a general purpose divider. A Synopsis-synthesized VHDL description of a parallel reciprocal circuit is included for comparison. Both realizations have been demonstrated in an adaptive sample rate notch filter which has been downloaded into a single Xilinx XC4010 reconfigurable Field Programmable Gate Array (FPGA).
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Strandberg, R.H., Bustamante, L.G., Oklobdzija, V.G. et al. Efficient realizations of squaring circuit and reciprocal used in adaptive sample rate notch filters. J VLSI Sign Process Syst Sign Image Video Technol 14, 303–309 (1996). https://doi.org/10.1007/BF00929623
- Field Programmable Gate Array
- Full Adder
- Residue Number System
- Computer Engineer Department
- Narrowband Interference