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Lower bounds on memory requirements for statically scheduled DSP programs

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Abstract

This paper presents novel techniques for computing the minimum number of memory locations in statically scheduled digital signal processing (DSP) programs. Two related problems are considered. In the first problem, we compute the minimum number of memory locations required for a scheduled program assuming that no circuit transformations (such as pipelining and retiming) are to be performed after scheduling. For this problem, we consider memory minimization for theoperation-constrained, processor-constrained andunconstrained memory models which represent various restrictions on how data can be allocated to memory. Then we consider the second problem, where memory minimization for a scheduled program is considered simultaneously with retiming using a variation of the retiming problem referred to as theminimum physical storage location (MPSL) retiming. While both problems consider memory minimization for scheduled programs, the second problem minimizes memory using retiming whereas the first problem performs no retiming. The scheduling results obtained from the MARS design system are used to compare memory requirements in the context of both of these problems. Our experiments show that MARS performs an optimal retiming for the schedule it generates. These memory requirements are then compared with an integer linear programming solution to the scheduling problem which is optimal under the unconstrained memory model. It is concluded that the schedule obtained by the MARS system achieves optimality or near-optimality with respect to register minimization.

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Denk, T.C., Parhi, K.K. Lower bounds on memory requirements for statically scheduled DSP programs. J VLSI Sign Process Syst Sign Image Video Technol 12, 247–264 (1996). https://doi.org/10.1007/BF00924988

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Keywords

  • Digital Signal Processing
  • Memory Model
  • Iteration Period
  • Live Variable
  • Time Partition