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Low-voltage CMOS subthreshold four-quadrant tripler

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Abstract

A CMOS four-quadrant tripler using transistors operated in the subthreshold region is presented. The goal of this circuit is to realize the product of three input signals. This circuit has been implemented in a 0.8 μm single-poly double-metal n-well CMOS process. Experimental results show that for a power supply of ±1.5V, the linear input range of this tripler is within ±100mV with the linearity error less than 2%. The total harmonic distortion is less than 2.5% with input range up to ±100mV. The-3dB bandwidth of this tripler is measured to be about 700 kHz.

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Liu, S., Chen, P. Low-voltage CMOS subthreshold four-quadrant tripler. Analog Integr Circ Sig Process 11, 303–307 (1996). https://doi.org/10.1007/BF00240491

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Keywords

  • Signal Processing
  • Power Supply
  • Input Signal
  • CMOS Process
  • Harmonic Distortion