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Signal Clustering Using Temporal Logics

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Runtime Verification (RV 2017)

Part of the book series: Lecture Notes in Computer Science ((LNPSE,volume 10548))

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Abstract

This paper introduces a new method for clustering signals using their temporal logic properties. Specifically, we propose a hierarchical clustering algorithm for efficiently processing a set of input signals. The input data is unlabeled, that is, no further information about properties of the signals are available to the learning algorithm other than the signals themselves. The algorithm produces a hierarchical structure where the internal nodes test some temporal properties of the data, and each terminal node contains a cluster (i.e., a group of similar signals). Each cluster can be mapped to a Signal Temporal Logic (STL) formula that describes its signals. The obtained formulae can be used directly for monitoring purposes but also, more generally, to acquire knowledge about the system under analysis. We present two case studies to illustrate the characteristics of our proposed algorithm. The first case study is related to a maritime surveillance problem, and the second is a fault classification problem in an automatic transmission system.

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Notes

  1. 1.

    A more general definition of the set \(\mathcal {F}\) is used in [19].

  2. 2.

    If the original sampling times of \(s^1\) and \(s^2\) are not the same, the signals can be re-interpolated to obtain values for matching sampling times.

  3. 3.

    We ran our experiments on a Windows PC with an Intel 5920K CPU.

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Acknowledgments

This work was partially supported by DENSO CORPORATION and by the Office of Naval Research under grant N00014-14-1-0554. The authors would like to acknowledge Hirotoshi Yasuoka (DENSO CORPORATION) and Rachael Ivison (Boston University) for providing valuable feedback during this research. We also thank the anonymous reviewers for their comments.

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Correspondence to Giuseppe Bombara .

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Bombara, G., Belta, C. (2017). Signal Clustering Using Temporal Logics. In: Lahiri, S., Reger, G. (eds) Runtime Verification. RV 2017. Lecture Notes in Computer Science(), vol 10548. Springer, Cham. https://doi.org/10.1007/978-3-319-67531-2_8

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  • DOI: https://doi.org/10.1007/978-3-319-67531-2_8

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