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Atomic Layer Deposition of Dielectrics on Graphene

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Graphene Nanoelectronics

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Abstract

Graphene, a monolayer of sp2 bonded carbon atoms, has recently attracted wide-spread attention because of its unique transport and physical properties that are appealing for a wide range of electronic applications. Integration with scalable high-κ dielectrics is important for the realization of graphene-based top-gated electronic devices including field effect transistors (FETs) and new logic device concepts. These gate dielectrics are expected to be thin (2–30 nm), with minimal trapped and mobile charges that otherwise would negatively affect device performance. In addition, the dielectrics are expected to enable operation at very high frequencies (including the THz range) needed for next generation radiofrequency applications, improve the channel mobility by screening charged impurities, and reduce the high leakage currents observed in traditional silicon dioxide (SiO2) gated devices.

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Acknowledgements

The authors thank L.O. Nyakiti, N. Nepal, R.L. Myers-Ward, J.K. Hite, G.G. Jernigan, and C.R. Eddy, Jr, for helpful discussions, and Dr. Eva Darian for providing Fig. 9.1(a). This work was supported by the Office of Naval Research. VDW is grateful for a postdoctoral fellowship from ASEE.

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Authors and Affiliations

  1. U.S. Naval Research Laboratory, Washington, DC, USA

    Nelson Y. Garces, Virginia D. Wheeler & D. Kurt Gaskill

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  1. Nelson Y. Garces
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  2. Virginia D. Wheeler
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  3. D. Kurt Gaskill
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Correspondence to Nelson Y. Garces .

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  1. , Nanotechnology Research Center, Georgia Institute of Technology, Atlantic Drive NW 791, Atlanta, 30332-0269, USA

    Raghu Murali

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Garces, N.Y., Wheeler, V.D., Gaskill, D.K. (2012). Atomic Layer Deposition of Dielectrics on Graphene. In: Murali, R. (eds) Graphene Nanoelectronics. Springer, Boston, MA. https://doi.org/10.1007/978-1-4614-0548-1_9

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  • DOI: https://doi.org/10.1007/978-1-4614-0548-1_9

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