Skip to main content
SpringerLink
Log in

The pRAM as a hardware-realisable neuron

  • Conference paper
Neural Network Applications

Part of the book series: Perspectives in Neural Computing ((PERSPECT.NEURAL))

Abstract

The pRAM is a non-linear stochastic device with neuron-like behaviour. The pRAM generates an output in the form of a spike train. The spike train may be integrated over a variable number of time steps to control the amount of noise in the system. The pRAM is realisable in hardware and VLSI devices have been built. Learning algorithms have been developed for the pRAM which may be incorporated in hardware and the intrinsic noise in the pRAM has proved beneficial during training. A current application of a pRAM net is in real-time object recognition.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

Similar content being viewed by others

References

  1. W S McCulloch and W Pitts, “A logical calculus of the ideas immanent in nervous activity”, Bulletin of Mathematical Biophysics, 5, 115–133, 1943.

    Article  MATH  MathSciNet  Google Scholar 

  2. I Aleksander, “Microcircuit learning computers”, Mills and Boon, London, 1971.

    MATH  Google Scholar 

  3. T G Clarkson, D Gorse and J G Taylor, “Hardware realisable models of neural processing”, Proc. 1st IEE Int. Conf. on Artificial Neural Networks, London, 242–246, 1989.

    Google Scholar 

  4. T G Clarkson, D Gorse and J G Taylor, “From wetware to hardware: reverse engineering using probabilistic RAMs”, Journal of Intelligent Systems, Freund, London, in press.

    Google Scholar 

  5. T G Clarkson, D Gorse and J G Taylor, “Biologically plausible learning in hardware realisable nets”, Proc. ICANN91 Conf., Helsinki, 195–199, 1991.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Department of Electronic and Electrical Engineering, King’s College London, UK

    T. G. Clarkson

Authors
  1. T. G. Clarkson
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Centre for Neural Networks, Department of Mathematics, King’ College, WC2R 2LS, Strand, London, UK

    J. G. Taylor BA, BSc, MA, PhD, FlnstP (Director) (Director)

Rights and permissions

Reprints and permissions

Copyright information

© 1992 Springer-Verlag London Limited

About this paper

Cite this paper

Clarkson, T.G. (1992). The pRAM as a hardware-realisable neuron. In: Taylor, J.G. (eds) Neural Network Applications. Perspectives in Neural Computing. Springer, London. https://doi.org/10.1007/978-1-4471-2003-2_11

Download citation

  • DOI: https://doi.org/10.1007/978-1-4471-2003-2_11

  • Publisher Name: Springer, London

  • Print ISBN: 978-3-540-19772-0

  • Online ISBN: 978-1-4471-2003-2

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation