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Method of high-level technology mapping based on knowledge(rule)

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Journal of Electronics (China)

Abstract

This paper studies the linkage problem between the result of high-level synthesis and back-end technology, presents a method of high-level technology mapping based on knowledge, and studies deeply all of its important links such as knowledge representation, knowledge utility and knowledge acquisition. It includes: (1) present a kind of expanded production about knowledge of circuit structure; (2) present a VHDL-based method to acquire knowledge of technology mapping; (3) provide solution control strategy and algorithm of knowledge utility; (4) present a half-automatic maintenance method, which can find redundance and contradiction of knowledge base; (5) present a practical method to embed the algorithm into knowledge system to decrease complexity of knowledge base. A system has been developed and linked with three kinds of technologies, so verified the work of this paper.

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References

  1. Ma Cong, Liu Mingye, et al., Linkage between VHDL high-level synthesis and bottom physical design, Acta Electronica Sinica, 26(1998)2, 71–73, (in Chinese).

    Google Scholar 

  2. R. Ang, N. Dutt, An algorithm for allocation of functional units from realistic RT component libraries, 7th Int. Symp. High-Level Synth., 1994, 164–169.

  3. E. A. Rundensteiner, D. D. Gajski, Component synthesis from function descriptions, IEEE Trans. on CAD, IC&Syst., 12(1993)9, 1287–1299.

    Google Scholar 

  4. Liu Mingye, et al., Theory of High Level Synthesis for ASIC, Beijing, Beijing Institute of Technology Press, 1997, 179–238, 307–366, (in Chinese).

    Google Scholar 

  5. R. K. Brayton, R. Camposano, et al., The Yorktown Silicon Compiler, In Silicon Compilation, D. D. Gajski(Ed.), Addison-Wesley, Reading, MA, 1988, 204–311.

    Google Scholar 

  6. G. D. Chen, D. D. Gajski, An intelligent component database for behavioral synthesis. Proc. of the 27th Design Automation Conference, IEEE/ACM, Orlando Florida, 1990, 150–155.

    Chapter  Google Scholar 

  7. N. V. Zanden, G. D. MILO, A microarchitecture and logic optimizer, Proc. of the 25th Design Automation Conference, IEEE/ACM, Anaheim Convevtion Center, 1988, 403–408.

  8. A. R. Baseer, M. Balakreshnan, et al., FAST: FPGA targeted RTL structure synthesis technique, 7th International Conference on VLSI Design Calcutta, India, Jan 1994.

  9. A. R. Naseer, M. Balakrishnan, et al., Delay minimal mapping RTL structures onto LUT based FPGAs, Field programmable logic and applications, 5th International Workshop, FPL’95, Proc., Oxford, UK, 29 Aug–1 Sept, 1995, 139–141.

  10. M. Vootukuru, R. Vemuri, et al., Resource constrained RTL partition for synthesis of multi-FPGA designs, Proc. of the Tenth International Conference on VLSI Design, Hyderabad, India, 4–7 Jan, 1997, 140–144.

  11. Sri Parameswaran, M. F. Schulz, Computer-aided selection of components for technology-independent specifications, IEEE Trans. on Comput-Aided Des. Integr. Circuits Syst., 13(1994)11, 1333–1350.

    Article  Google Scholar 

  12. P. K. Jha, N. D. Dutt, High-level library mapping for arithmetic components, IEEE Trans. on VLSI Syst., 4(1996)2, 157–169.

    Article  Google Scholar 

  13. Ma Cong, Wang Zuojian, Liu Mingye, Strategy and implementation of high-level, Multi-object technology mapping in high-level synthesis, Chinese Journal of computer, 22(1999)9, 975–980.

    Google Scholar 

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Ma, C., Wang, Z. & Liu, M. Method of high-level technology mapping based on knowledge(rule). J. of Electron.(China) 18, 24–31 (2001). https://doi.org/10.1007/s11767-001-0004-9

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  • DOI: https://doi.org/10.1007/s11767-001-0004-9

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